The invention relates to a test circuit such as a built-in self test (hereinafter referred to as BIST) circuit and the like provided with two group of clocks which are different in frequency for testing a circuit to be tested such as a high-speed semiconductor memory and the like, and a semiconductor integrated circuit such as a control chip, a system large scaled integrated circuit (hereinafter referred to as system LSI) and the like, in which the test circuit is built in, and a method of testing the same.
A technology relating to a conventional BIST serving as one of test circuits for testing a semiconductor integrated circuit and the like has been disclosed in JP-A H10-199294, JP-A 2002-174662.
The BIST circuit is a circuit for generating commands of a circuit to be tested (e.g., Synchronous Dynamic Random Access Memory serving as one of semiconductor memories, hereinafter referred to as “SDRAM”), and it is used, for example, when connected to a tester.
The BIST circuit has a BIST control circuit, and a pattern generation circuit and a data comparator are connected to an output of the BIST control circuit, respectively. An output control circuit is connected to an output of the data comparator. These BIST control circuit, pattern generation circuit, data comparator, and output control circuit are formed on the same semiconductor substrate, respectively.
A test clock outputted from the tester has, e.g., about 40 MHz, and all the circuit blocks inside the BIST circuit operate in synchronization with the test clock, respectively. A clock outputted from the pattern generation circuit is synchronous with the test clock, and has a frequency which is not more than that of the test clock, and the SDRAM is tested in response to this clock.
For example, in cases where an SDRAM to be tested for use in high-speed operation and has an actual operating frequency not less 100 MHz which is faster than the frequency of the test clock, the high-speed SDRAM can not be tested with an actual operating frequency using a low speed tester.
That is, in cases where the high-speed SDRAM is intended to be tested by the conventional BISI circuit with the actual operating frequency exceeding the test clock, the SDRAM can not be tested so far.
Accordingly, when a high-speed SDRAM is to be tested, a high-speed tester capable of generating a high-speed test clock corresponding thereto, and of processing a high-speed test data output signal is needed. However, the speeding up of the semiconductor integrated circuit such as an SDRAM and the like has recently made rapid progress, and hence if a tester is prepared in accordance therewith, cost of equipment has increased and also training for making full use of the tester is needed, resulting in disadvantage and inconvenience.